Verification startup’s patent-pending engine targets 100x faster full-chip simulation,
giving chip teams a path back from expensive hardware emulation
Tel Aviv, Israel — July 27, 2026
Hiveware, a deep-tech EDA company building a next-generation SystemVerilog simulator, today announced its emergence from stealth with $24 million in Series A funding led by RTP Global. The company’s patent-pending digital-simulation platform – currently in pilot with three of the world’s largest semiconductor companies– is being designed from first principles for the scale and complexity of modern SoC development.
A verification crisis decades in the making
For more than three decades, the fundamental architecture of digital simulation tools has remained largely unchanged. The verification approach that was adequate when SoCs numbered in the millions of transistors, is hitting the runtime wall.
As chip designs have scaled toward hundreds of billions of transistors – incorporating complex CPU clusters, AI accelerator logic, high-speed interfaces and hundreds of millions of lines of embedded software, fullchip simulation runtimes have stretched from hours into days or weeks. The result is a growing reliance on hardware emulation platforms that can cost hundreds of millions of dollars, offer limited debug visibility and require complex setup procedures. In addition, engineering teams often have limited access to emulation tools, and, when they do, the machines might cover just a subset of full chip and software tests.
In short,the tools have not kept pace with the silicon, as verification has moved onto the critical path to tape-out. That is the problem Hiveware was built to solve.
A clean-sheet architecture built for modern SoC scale
Because the Hiveware team is building the simulation foundation from scratch, the technology can optimize design-under-test (DUT) overhead that burdens traditional simulation at scale. The practical result is up to 10x faster full-chip simulation on standard server infrastructure, on-premises or in the cloud, with a roadmap toward 100x.
Critically, Hiveware’s technology requires no specialized hardware and is fully compatible with existing SystemVerilog design environments. For engineering teams currently relying on emulation platforms to handle full-chip workloads, it offers a path to bring those workloads back into software simulation, with greater debug visibility, faster iteration cycles, and substantially lower cost.
“Advanced chip teams have been managing around the simulation problem for years, throwing emulation hardware at it, or accepting that full-chip verification takes longer than it should,” said Ohad Agami, CEO and co-founder of Hiveware. “We didn’t set out to incrementally improve an existing tool. We asked what a simulator designed from scratch for the realities of modern SoC development would look like and built that. The funding and the patent will give us the foundation to bring it to market.”
Funding and early validation
The $24 million Series A round supports continued development of the Hiveware engine, expansion of the engineering team and commercial engagements with enterprise semiconductor customers. Hiveware has a team of 30 people, including 25 engineers, and is currently working with several large semiconductor enterprises to deploy into their workflows.
“Every era of computing eventually runs into the limits of the tools that build it. In chip design, that limit is verification. It has barely moved in a decade, and it now sits between every design and the factory. Ohad, Yaniv and the Hiveware team have the technical depth, and the trust of serious customers, to change that. Solving a bottleneck this fundamental is how lasting companies get built, and the stakes only climb as AI pushes chip complexity further.” said Nishit Garg, Partner at RTP Global who led the Series A.
“Speed only matters if the result can be trusted”, said Yaniv Pascal, CTO and co-founder of Hiveware. “The engineering challenge isn’t just performance, it’s building a simulation engine that adapts to what a modern SoC actually demands: overnight regression runs, fast incremental compile cycles, deep debug visibility on workloads that were previously only a fit for emulation. That’s what the architecture was designed for.”
Leadership
Hiveware was co-founded by Ohad Agami (CEO) and Yaniv Pascal (CTO), semiconductor industry veterans whose experience spans elite technology units and advanced chip development at companies including Hailo, a leading AI semiconductor company, where both led complex verification flows and architectures. The company’s commercial leadership includes Ronen Laviv, VP of Product, whose career spans nearly a decade driving large-scale verification deployments at Cadence and helping semiconductor companies transition EDA workloads to the cloud at AWS.
The company is backed by RTP Global and is a portfolio company of Intel Ignite, Intel’s global startup accelerator.
DAC 2026
Hiveware will be available for press and analyst briefings at DAC 2026 in Long Beach, California, July 26–29.
About Hiveware
Hiveware is a deep-tech EDA company building a new foundation for digital SoC simulation. Its patent-pending technology platform aims to deliver a performance boost of up to 100x faster full-chip verification on standard server infrastructure. Designed for the scale and complexity of modern chip development, Hiveware’s technology gives verification teams a faster, more scalable path from architecture to tape-out without the cost or debug constraints of hardware emulation. Hiveware is headquartered in Tel Aviv, Israel, and backed by $24 million in Series A funding.
About RTP Global
RTP Global is an early-stage venture capital firm, backing the founders who use technology to reimagine how the world works. Since 2000, RTP Global has made over 150 investments worldwide, with one in 10 becoming multi-billion dollar companies and one in 20 publicly trading at over $10bn. Notable investments include Datadog, DeliveryHero, Cred and SumUp. RTP Global has offices in New York, London, Paris, Dubai and Bangalore.
Media Contact :
Michelle Clancy Fuller, Cayenne Global, +1 503.702.4732
